Authors:	W. Bogaerts, Y. Xing, Y. Ye, U. Khan, J. Dong, J. Geessels, M. Fiers, D. Spina, T. Dhaene
Title:	Predicting Yield of Photonic Circuits With Wafer-scale Fabrication Variability
Format:	International Conference Proceedings
Publication date:	5/2019
Journal/Conference/Book:	2019 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO) (invited)
Editor/Publisher:	IEEE,
Volume(Issue):	p.1-3
Location:	Boston, United States
DOI:	10.1109/NEMO.2019.8853660
Citations:	Look up on Google Scholar
Download:	(1MB)

Abstract

We present a workflow for variability analysis and yield prediction of photonic integrated circuits affected by fabrication variations. The technique combines synthetic wafer maps with layout-aware Monte-Carlo simulations. We demonstrate this on different layout configurations of linewidth-tolerant Mach-Zehnder interferometers.

Related Research Topics

• Integration of photonic design tools
• Tolerant silicon photonic microcircuits
• Variability Aware Design

Related Projects

• FWO: G013815N-ScaleModel (Scalable behavioral models for large-scale silicon photonics)
• VLAIO: MEPIC (Model extraction to enable first-time right photonics integrated circuit design)