| Authors: | A. Naughton, J. Browne, M. Wallace, A. Wall, C. Browning, G. Koziuk, K. De Bruyn, J. Bauwelinck, M. Vanhoecke, A. Karmakar, L. Bogaert, G. Roelkens, D. Mackey | | Title: | 56 Gbps CPO silicon photonics transceiver with radiation-hardened electronics for CPO HSSL on satellite payloads | | Format: | International Conference Proceedings | | Publication date: | 7/2025 | | Journal/Conference/Book: | International Conference on Space Optics — ICSO 2024
| | Location: | Antibes Juan-les-Pins, France | | DOI: | 10.1117/12.3075358 | | Citations: | Look up on Google Scholar
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Abstract
Satellite serial links for higher data throughput and higher frequency telecom payloads necessitate increased use of on board computer processing resulting in the emergence of optical interconnects as the preferred solution for digital payloads on board satellites. In particular, data rate increases have exacerbated the challenges associated with electrical domain interconnects where the transmission distances reduce significantly with increased bit rates. This has both limited the reach of SerDes lanes from ASICs while also resulting in the need for more complex modulation formats and increased DSP, both of which result in increased power consumption. Optical interconnects also benefit from reduced mass and immunity to EMI. To date, optical transceivers for satellite payloads have focused on midboard VCSEL based technology with first generation transceivers at 12.5 Gb/s1 demonstrated in orbit and second generation devices targeting 25 Gb/s expected to be demonstrated next. However, in a similar trend to terrestrial data centers, the data rates are now increasing to a level which is challenging for directly modulated VCSELs while the move to more common comms wavelengths in the O- and C-band also presents many advantages. Co-packaged optics (CPO) is the emerging standard for terrestrial data center applications and there is an opportunity to adopt a similar architecture for satellite payloads. CPO targets the integration of optical transceivers very close to the functional ASIC/FPGA, thus enabling the use of lower power short reach SerDes and facilitating higher data rate transmission, while maintaining signal integrity and mitigating EMI effects. Related Projects
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